XTS-4802G is a high performance, wire speed Layer 2 Ethernet Switch that supports 48 10/100Mbps ports for downlinks and 2 10/100/1000Mbps ports for uplinks in a single ASIC.

For managed switch application, the combination of MIB counters, port-based VLAN, and external CPU for read/write of packets and NWay registers supported by XTS-4802G make it possible for user to disable/enable ports, disable/enable broadcast throttling, change speed and duplex mode, change VLAN port mapping remotely.

XTS-4802G supports hardware-based NWay, this enables it to make NWay change much faster than software-based solutions and eliminates the need for software development.

XTS-4802G is fully compliant with IEEE802.3x for flow control in full duplex mode. Flow control in half duplex mode is supported using backpressure algorithm. The amount of bandwidth consumed by broadcast on any given segment can be controlled by broadcast filtering to prevent abnormal broadcast activity from disrupting network performance.

XTS-4802G is a low power consumption device. The amount of heat generated is low enough to be dissipated via heat sink. No forced cooling fan is required.

·  Non-blocking wire-speed forwarding and filtering (13.6Gbps throughput)

·  Supports broadcast storm filtering control

·  Support up to 50 VLAN group for port-based VLAN

·  Support 5 sets of simple MIB counters (Rx Frame / Tx Frame / CRC Err) for diagnostics and statistics

·  Single external 25MHz clock source

·  No forced cooling fan required for heat dissipation

·  48 10/100Mbps + 2 10/100/1000Mbps port layer-2 Ethernet switch with embedded lookup table and packet buffer

·  Supports SSSMII on 10/100Mbps ports

·  Supports MII, GMII, or TBI on Gigabit ports:

    ■ Complies with 802.3z and 802.3ab

    ■ Full Duplex for MII, GMII, and TBI

    ■ Built-in PCS for SERDES transceiver

·  Built-in 8K entry MAC address look up table with auto-aging and auto-learning capabilities

·  Built-in 3.7Mbit SSRAM with 0.5Mbit for MAC address loop up table and 3.2Mbits for packet buffer

·  Store and forward architecture and head-of-line blocking prevention

·  All ports support Speed, Duplex, and 802.3x flow control ability auto-negotiation

·  Supports 802.3x full duplex flow control and backpressure half duplex flow control

·  Supports PHY register read/write access

·  8051 CPU interface

·  LED interface for Gigabit ports (Rx Active / Tx Active / Link Status)

·  0.18 µm, 1.8V core, 3.3V (5V tolerant) I/Os

·  272-pin PBGA package